[CS] Natalia Nottingham MS PresentationFeb 11, 2026

[via cs]

This is an announcement of Natalia Nottingham's MS Presentation
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Candidate: Natalia Nottingham

Date: Wednesday, February 11, 2026

Time: 11 am CST

Remote Location: URL: https://uchicago.zoom.us/j/92170741933?pwd=jMCUKW61e10Y5WwLHijuI1fMBqXlc0.1&from=addon Meeting ID: 921 7074 1933 Password: 854487

Location: JCL 223

Title: Circuit decompositions and scheduling for neutral atom devices with limited local addressability

Abstract: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=10821351

    Despite major ongoing advancements in neutral atom hardware technology, there remains limited work in systems-level software tailored to overcoming the challenges of neutral atom quantum computers. In particular, most current neutral atom architectures do not natively support local addressing of single-qubit rotations about an axis in the xy-plane of the Bloch sphere. Instead, these are executed via global beams applied simultaneously to all qubits. While previous neutral atom experimental work has used straightforward synthesis methods to convert short sequences of operations into this native gate set, these methods cannot be incorporated into a systems-level framework nor applied to entire circuits without imposing impractical amounts of serialization. Without sufficient compiler optimizations, decompositions involving global gates will significantly increase circuit depth, gate count, and accumulation of errors. No prior compiler work has addressed this, and adapting existing compilers to solve this problem is nontrivial. 
    In this work, we present an optimized compiler pipeline that translates an input circuit from an arbitrary gate set into a realistic neutral atom native gate set containing global gates. We focus on decomposition and scheduling passes that minimize the final circuit’s global gate count and total global rotation amount. As we show, these costs contribute the most to the circuit’s duration and overall error, relative to costs incurred by other gate types. Compared to the unoptimized version of our compiler pipeline, minimizing global gate costs gives up to 4.77x speedup in circuit duration. Compared to the closest prior existing work, we achieve up to 53.8x speedup. For large circuits, we observe a few orders of magnitude improvement in circuit fidelities.


Advisors: Fred Chong
Committee Members: Fred Chong, Robert Rand, Jonathan Baker