[Colloquium] Reminder [masters-presentation] Duckering/MS Presentation/Apr 15, 2020

[Margaret Jaffey]

This is a reminder about Casey Duckering's MS Presentation tomorrow.

Here is the Zoom link to participate (including the event password):


https://uchicago.zoom.us/j/742056738?pwd=Y1dVZUMra3ExN1ZLOE5vTXh0UU1KZz09

Meeting ID: 742 056 738

Password: 007335

One tap mobile +13126266799,,742056738# US (Chicago)

Dial by your location +1 312 626 6799 US (Chicago)



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Date:  Wednesday, April 15, 2020

Time:  10:00 AM

Place:  remotely via Zoom

M.S. Candidate:  Casey Duckering

M.S. Paper Title: Virtualized Logical Qubits

Abstract:
Current, near-term quantum devices have shown great progress in the
last several years culminating recently with a demonstration of
quantum supremacy. These devices, however, are extremely limited with
prohibitively large error rates and therefore they have relatively few
applications. Many of the most anticipated quantum algorithms such as
Shor's and Grover's require fault tolerant logical qubits which are
built from large numbers of noisy, physical qubits and errors are
corrected via quantum error correction codes such as the surface code.
While current work on NISQ-era devices is important, there is
simultaneously a need to develop architectures for larger scale use of
systems composed of error corrected logical qubits.

In this work, we introduce an architecture matching a recent qubit
memory technology with established error correction designed without
memory in mind. We provide a new method for the virtualization of
error-corrected, logical qubits implemented with surface code patches.
Surface codes are promising error correction codes which only require
physical qubits with local, nearest-neighbor connectivity which is a
common feature among current leading superconducting quantum hardware.
Traditionally, surface code patches were arranged on this
two-dimensional grid. Recent hardware advances have demonstrated the
ability to store qubits in the resonant modes of superconducting
cavities attached to transmons and interactions between qubits in the
cavity are mediated via the transmon. This memory-like technology
enables a new 2.5D architecture which we demonstrate allows logical
qubits to be stored and can be paged in and out of memory as needed,
essentially virtualizing the logical qubits.

We demonstrate how traditional representations of surface code patches
can be implemented on our new system and show how operations in the
lattice-surgery-based surface code translate to our system.
Specifically, our system allows for transversal application of CNOT
operations between logical qubits sharing the same set of transmons
(same physical address) and can use either transversal or standard
lattice surgery CNOTs between logical qubits of different physical
addresses. These transversal CNOTs are 6x faster than standard lattice
surgery CNOTs. Our system can achieve fault tolerance comparable to
conventional two-dimensional grids while saving substantial hardware.
Furthermore, our architecture can produce magic states at 1.22x the
baseline rate given a fixed number of transmon qubits. This is a
critical benchmark for future fault-tolerant quantum computers, as
magic states are essential and machines will spend the majority of
their resources continuously producing them. This architecture will
reduce the hardware requirements for fault tolerant quantum computing
and experimentalists should consider it for early experimental
demonstrations.

Casey's advisor is Prof. Frederic Chong

Login to the Computer Science Department website for details:
 https://newtraell.cs.uchicago.edu/phd/ms_announcements#cduck

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Margaret P. Jaffey            margaret at cs.uchicago.edu
Department of Computer Science
Student Support Rep (JCL 350)              (773) 702-6011
The University of Chicago      http://www.cs.uchicago.edu
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