[CS] Andronicus Samsundar Rajasukumar Candidacy Exam/Oct 22, 2025 **8:30am**

[via cs]

This is an announcement of Andronicus Samsundar Rajasukumar's Candidacy Exam.
===============================================
Candidate: Andronicus Samsundar Rajasukumar

Date: Wednesday, October 22, 2025

Time:  **8:30 am CST**

Remote Location:  https://uchicago.zoom.us/j/98393108953?pwd=12XSAbaoaNx956b3O8BhrfGwE95BjW.1   
Meeting ID: 983 9310 8953 , Passcode: 340952

Location: JCL 298

Title: UpDown: An Effective, efficient and scalable Processing Near Memory architecture for irregular applications

Abstract : The significant growth in the scale of data processing has made large on-chip caches (∼0.5GB), in modern CPUs, ineffective in preventing long latency off-chip DRAM accesses to ease data-movement bottlenecks. Consequently, there has been a push for rapid innovation to find alternatives to the traditional Von Neumann architecture. Processing NearMemory (PNMs) architectures push compute logic in proximity to DRAM. They have direct access to data in DRAM sub-arrays (ranks, banks, channels) without traversing the CPU caches. This allows these cores to utilize the higher parallelism (and bandwidth) available at the bank/rank/channel interfaces. Some application specific PNMs have shown benefits on narrow domains where bulk memory operations are accelerated on dense, regular data. 

However, for the broader class of non-regular non-dense applications, PNMs face a number of issues. First, they lack access to all memory due to local address spaces. Second, there is lack of interaction with coherence and consistency mechanisms leading to inefficient workarounds. Third, there is a lack of efficient communication mechanisms for synchronization and coordination between all the PNM cores in a system. These issues make data movement and synchronization ineffective and inefficient on PNMs resulting in poor performance scaling, especially on irregular applications. Besides, local address spaces, explicit data movement and lack of interaction with coherence make programming PNMs extremely challenging.

We propose UpDown: a general-purpose Processing Near Memory architecture that attempts to address these issues with 4 novel features -Scalable-Memory Level Parallelism, Software Controlled Locality, ScalableMessage-Driven Synchronization and Fine-Grained Computations. In this proposal, we describe the innovative architectural mechanisms that enable these features.We also describe how these mechanisms can be implemented in a simple in-order core to create an efficient and scalable building block for large scale PNMs. We outline our research plan to evaluate the impact of these mechanisms and features using a set of irregular and regular applications and compare the performance and cost (area, energy and power) with traditional CPU architectures and current PNMs. We will demonstrate that across these applications, UpDown can achieve efficient, scalable data movement and synchronization. With flexible and general programmability we also expect to show that UpDown can achieve overall performance benefits on these applications compared to traditional multi-core CPUs (> 100x) and current PNMs (> 4x).

Advisor: Andrew Chien 

Committee Members: Andrew Chien, Fred Chong, Valerie Taylor