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<i><span style="font-size: 12pt; font-family: Helvetica; color: rgb(139, 1, 2);">UNIVERSITY OF CHICAGO</span></i><o:p></o:p></p>
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<i><span style="font-size: 12pt; font-family: Helvetica; color: rgb(139, 1, 2);">COMPUTER SCIENCE DEPARTMENT</span></i><o:p></o:p></p>
<div style="font-family: Helvetica;"><i style="font-family: Calibri, sans-serif; font-size: 10pt;"><span style="font-size: 12pt; font-family: Helvetica; color: rgb(139, 1, 2);">PRESENTS</span></i></div>
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<div class="elementToProof"><b><font size="5">Deming Chen</font><span class="Apple-tab-span" style="font-size: medium; white-space: pre;">
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<b>University of Illinois Urbana-Champaign</b></div>
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<b>Friday, March 7, 2025 at 1:30pm</b></div>
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<b>Location: JCL 390</b></div>
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<b>Title: Fully Automated PyTorch-to-Accelerator Design Flow</b> </div>
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<b style="font-size: 12pt;">Abstract: </b><span style="background-color: white; font-size: 11pt;">In this talk, we introduce a new design flow, ScaleHLS, that established a new High-Level Synthesis (HLS) solution translating AI models described in PyTorch to
customized AI accelerators automatically. By adopting PyTorch as input for AI designs (instead of traditional C/C++ for HLS), the lines of code and design simulation time can be reduced by about 10× and 100×, respectively. </span><span style="background-color: white; font-size: 11pt;">Meanwhile,
despite being fully automated and able to handle various applications, this new flow achieves a 1.29x higher throughput over DNNBuilder, a state-of-the-art RTL-based neural network accelerator on FPGAs.</span><span style="background-color: white; font-size: 11pt;"> Such
AI model-to-RTL flows pave the way for a new wave of HLS that could drive the high-productivity designs of AI circuits with high density, high-energy efficiency, low cost, and short design cycle. Meanwhile, we are also facing existing and new challenges for
such HLS solutions, such as ensuring the correctness of the high-level design, accommodating accurate low-level timing/energy information, handling the complexity of 3D circuits and/or chiplet-based design flows, and achieving all these in a highly scalable
manner.</span></div>
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<b style="font-size: 12pt;">Bio: </b><span style="font-size: 14.666667px; background-color: rgb(255, 255, 255);">Deming Chen is the Abel Bliss Professor in the Grainger College of Engineering at the University of Illinois Urbana-Champaign. His research interests
include hybrid cloud systems, machine learning and AI, reconfigurable and heterogeneous computing, security and confidential computing, and system-level design methodologies. He has published over 290 research papers, received 10 Best Paper Awards and an ACM/SIGDA
TCFPGA Hall-of-Fame Paper Award, and delivered more than 160 invited talks. His work has had a significant impact, with open-source solutions adopted by industry, such as FCUDA, DNNBuilder, CSRNet, SkyNet, ScaleHLS, and Medusa. Notably, Medusa has been integrated
into Nvidia's TensorRT-LLM, improving the speed of large language model (LLM) execution by 1.9-3.6x. He is an IEEE Fellow, an ACM Distinguished Speaker, and the Editor-in-Chief of ACM Transactions on Reconfigurable Technology and Systems (TRETS). Under his
leadership, the impact factor of ACM TRETS has increased by 3.8 times. He serves as the Illinois Director of the IBM-Illinois Discovery Accelerator Institute and the Director of the AMD-Xilinx Center of Excellence. Additionally, he has been involved in several
startup companies, including AutoESL and Inspirit IoT. He received his Ph.D. in Computer Science from UCLA in 2005.</span></div>
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<b style="font-size: 14px;">Host: Yanjing Li </b></div>
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