<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class=""><div class=""><i class=""><b class="">Department of Computer Science Seminar</b></i></div><div class=""><b class=""><br class=""></b></div><div class="">
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<div class="column"><p class=""><span style="font-size: 14px;" class="">Thomas Sterling </span></p>
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<div class="column"><p class=""><span style="font-size: 14px;" class="">Professor of Intelligent Systems Engineering
School of Informatics, Computing, and Engineering</span></p><p class=""><span style="font-size: 14px;" class="">Indiana University </span></p>
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</div></div><div class=""><b class="">Thursday, January 19th</b></div><div class=""><b class="">1:00pm - 2:00pm</b></div><div class=""><b class="">Crerar Library 298</b></div><div class=""><b class=""><br class=""></b></div><div class=""><b class="">Active Memory
Architecture: memory-centric non von Neumann Dynamic Graph Processing</b></div></div><div class="">
<!--EndFragment--><br class=""><b class="">Abstract: </b>A revolution in scalable computer system design is emerging
in the domains of Machine Learning, Data Analytics, and Graph Processing. Leaders
in the commercial field (e.g., Google) and energetic startups (e.g., Graphcore)
with combined assets in the billions of dollars are pushing the boundaries of
these perceived market opportunities through R&D in computer architecture,
API models, and software. The new IARPA AGILE research program has been created
to advance the state-of-the-art beyond these near-term commercial techniques with
the University of Chicago and Indiana University among the recently selected
performers. The 3-year AGILE program, recently undertaken, seeks major
innovations in architecture, runtime software, and parallel algorithms to
achieve one to two orders of magnitude performance gains within this decade for
capabilities in graph-data and machine intelligence. The experimental Active
Memory Architecture is an innovative memory centric non von Neumann system
concept devised to circumvent legacy bottlenecks of traditional von
Neumann-based cores and develop smart memories to accelerate primitive
operations central to graph execution including irregular time-varying data
structures. This seminar will describe work-in-progress for the innovative
Active Memory Architecture (AMA) to meet these challenging goals for Machine
Intelligence in its diversity of forms. AMA is conceived to deliver dramatic
capability gains in dynamic graph computation and is combined with the proposed
system-wide Pilot-CRIS scalable structure for full-graph capacity handling. Qualitative
justification will be discussed to motivate adoption of the AMA conceptual
strategy. Questions and comments will be welcome from the audience throughout
the technical presentation.</div><div class=""><p class="MsoNormal"><o:p class=""></o:p></p><p class="MsoNormal"><b class="">Bio:</b>Thomas Sterling is a Full Professor of Intelligent Systems Engineering at Indiana
University (IU) serving as Director of the AI Computing Systems Laboratory at IU’s
Luddy School of Informatics, Computing, and Engineering. Since receiving his Ph.D
from MIT as a Hertz Fellow in 1984, Dr. Sterling has engaged in applied research in
parallel computing system structures, semantics, and operation in industry, government
labs, and academia. Professional affiliations have included Harris Corp., IDA
Supercomputing Research Center, NASA (GSFC, JPL), Un. of Maryland, Caltech, and
LSU. Dr. Sterling is best known as the "father of Beowulf" for his pioneering research in
commodity/Linux cluster computing for which he shared the Gordon Bell Prize in 1997.
His current research is associated with innovative extreme scale computing through
memory-centric non von Neumann architecture concepts to accelerate dynamic graph
processing for AI including ML. In 2018, he co-founded the new tech company, Simultac
LLC, and serves as its President and Chief Scientist. Dr. Sterling was the recipient of
the 2013 Vanguard Award and is a Fellow of the AAAS. He has been selected this year
to be inducted in the Space Technologies Hall of Fame. He is the co-author of seven
books and holds six patents. Most recently, he co-authored the introductory textbook,
“High Performance Computing”, published by Morgan-Kaufmann in 2018 which is going
into 2<span style="vertical-align: 4pt;" class="">nd </span>edition. </p></div><div class=""><br class=""></div><div class=""><img apple-inline="yes" id="EFF8E459-E1D9-42F0-A19D-B80839343687" src="cid:C0C6026B-688E-465C-90E4-FA1C7E317678" class=""></div><div class=""><br class=""></div><div class=""><br class=""></div><div class=""><b class="">Host</b>: Andrew A. Chien</div><div class=""><br class=""></div><div class=""><br class=""></div><div class=""><br class=""></div><div class=""><br class=""></div></body></html>