<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div>This is an updated announcement of Casey Duckering's MS Presentation.<br class=""><br class="">Here is the Zoom link to participate:<br class=""><br class=""><a href="https://uchicago.zoom.us/j/742056738" class="">https://uchicago.zoom.us/j/742056738</a><br class=""><br class="">Meeting ID: 742 056 738<br class=""><br class="">One tap mobile +13126266799,,742056738# US (Chicago)<br class=""><br class="">Dial by your location +1 312 626 6799 US (Chicago)<br class=""><br class=""><br class=""><br class="">------------------------------------------------------------------------------<br class="">Date: Wednesday, April 15, 2020<br class=""><br class="">Time: 10:00 AM<br class=""><br class="">Place: remotely via Zoom<br class=""><br class="">M.S. Candidate: Casey Duckering<br class=""><br class="">M.S. Paper Title: Virtualized Logical Qubits<br class=""><br class="">Abstract:<br class="">Current, near-term quantum devices have shown great progress in the<br class="">last several years culminating recently with a demonstration of<br class="">quantum supremacy. These devices, however, are extremely limited with<br class="">prohibitively large error rates and therefore they have relatively few<br class="">applications. Many of the most anticipated quantum algorithms such as<br class="">Shor's and Grover's require fault tolerant logical qubits which are<br class="">built from large numbers of noisy, physical qubits and errors are<br class="">corrected via quantum error correction codes such as the surface code.<br class="">While current work on NISQ-era devices is important, there is<br class="">simultaneously a need to develop architectures for larger scale use of<br class="">systems composed of error corrected logical qubits.<br class=""><br class="">In this work, we introduce an architecture matching a recent qubit<br class="">memory technology with established error correction designed without<br class="">memory in mind. We provide a new method for the virtualization of<br class="">error-corrected, logical qubits implemented with surface code patches.<br class="">Surface codes are promising error correction codes which only require<br class="">physical qubits with local, nearest-neighbor connectivity which is a<br class="">common feature among current leading superconducting quantum hardware.<br class="">Traditionally, surface code patches were arranged on this<br class="">two-dimensional grid. Recent hardware advances have demonstrated the<br class="">ability to store qubits in the resonant modes of superconducting<br class="">cavities attached to transmons and interactions between qubits in the<br class="">cavity are mediated via the transmon. This memory-like technology<br class="">enables a new 2.5D architecture which we demonstrate allows logical<br class="">qubits to be stored and can be paged in and out of memory as needed,<br class="">essentially virtualizing the logical qubits.<br class=""><br class="">We demonstrate how traditional representations of surface code patches<br class="">can be implemented on our new system and show how operations in the<br class="">lattice-surgery-based surface code translate to our system.<br class="">Specifically, our system allows for transversal application of CNOT<br class="">operations between logical qubits sharing the same set of transmons<br class="">(same physical address) and can use either transversal or standard<br class="">lattice surgery CNOTs between logical qubits of different physical<br class="">addresses. These transversal CNOTs are 6x faster than standard lattice<br class="">surgery CNOTs. Our system can achieve fault tolerance comparable to<br class="">conventional two-dimensional grids while saving substantial hardware.<br class="">Furthermore, our architecture can produce magic states at 1.22x the<br class="">baseline rate given a fixed number of transmon qubits. This is a<br class="">critical benchmark for future fault-tolerant quantum computers, as<br class="">magic states are essential and machines will spend the majority of<br class="">their resources continuously producing them. This architecture will<br class="">reduce the hardware requirements for fault tolerant quantum computing<br class="">and experimentalists should consider it for early experimental<br class="">demonstrations.<br class=""><br class="">Casey's advisor is Prof. Frederic Chong<br class=""><br class="">Please contact Margaret Jaffey (<a href="mailto:margaret@cs.uchicago.edu" class="">margaret@cs.uchicago.edu</a>) to request</div><div>a draft copy of Casey Duckering’s MS paper.</div><div><br class="">=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=<br class="">Margaret P. Jaffey margaret at <a href="http://cs.uchicago.edu" class="">cs.uchicago.edu</a><br class="">Department of Computer Science<br class="">Student Support Rep (JCL 350) (773) 702-6011<br class="">The University of Chicago <a href="http://www.cs.uchicago.edu" class="">http://www.cs.uchicago.edu</a><br class="">=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=<br class="">_______________________________________________<br class="">Colloquium mailing list - <a href="mailto:Colloquium@mailman.cs.uchicago.edu" class="">Colloquium@mailman.cs.uchicago.edu</a><br class=""><a href="https://mailman.cs.uchicago.edu/mailman/listinfo/colloquium" class="">https://mailman.cs.uchicago.edu/mailman/listinfo/colloquium</a><br class="">_______________________________________________<br class="">Phd-students mailing list<br class="">Phd-students@mailman.cs.uchicago.edu<br class="">https://mailman.cs.uchicago.edu/mailman/listinfo/phd-students<br class=""></div></body></html>