[Colloquium] Reminder: Three Workshops on Parallel Programming from Intel

[Benjamin Recchie]

Please forward this workshop announcement to your faculty, students, and colleagues who may be interested.


Three Workshops on Parallel Programming from Intel

Intel Software for High-Performance Parallel Applications

Wednesday, May 20, 2015, 9:00 a.m. to 5:00 p.m. | Kathleen A. Zar Room, John Crerar Library

In this workshop, you will be introduced to Intel Parallel Studio XE Cluster Edition, a multi-component software toolkit to create parallel applications, with a focus on trace collection and analysis. You will also be introduced to Intel compilers, along with Intel's performance and threading analysis tools, such as Intel VTune Amplifier, Intel Inspector, and Intel Advisor. Finally, you will be introduced to the Intel Math Kernel Library, a math library specially designed for high performance on Intel processors.

Register for this workshop here<https://training.uchicago.edu/course_detail.cfm?course_id=1550>.

Parallel Programming and Optimization with Intel Xeon Phi Coprocessors: CDT 101

Thursday, May 21, 2015, 9:30 a.m. to 4:30 p.m. | Kathleen A. Zar Room, John Crerar Library

This one-day training provides software developers the foundation needed for modernizing their codes to extract more of the parallel compute performance potential found in both Intel Xeon processors and Intel Xeon Phi coprocessors.


The session will cover:

  *   MIC architecture: purpose, organization, pre-requisites for good performance, future technology.
  *   Programming models: native, offload, heterogeneous clustering.
  *   Parallel frameworks: automatic vectorization, OpenMP, MPI.
  *   Optimization Methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics.

Register for this workshop here<http://events.r20.constantcontact.com/register/event?oeidk=a07eao1dixt534e0ac5&llr=kpiwi7pab>.


Parallel Programming and Optimization with Intel Xeon Phi Coprocessors: CDT 102

Friday, May 22, 2015, 9:30 to 4:30 p.m. | Kathleen A. Zar Room, John Crerar Library

This one-day training provides software developers the foundation needed for modernizing their codes to extract more of the parallel compute performance potential found in both Intel Xeon processors and Intel Xeon Phi coprocessors. It builds on information attendees will have learned in the previous day's workshop, CDT 101.


The session will cover:

  *
Offload and Native: “Hello World” to complex; using MPI.
  *
Performance Analysis: VTune.
  *
Case Study: all aspects of tuning in the N-body calculation.
  *
Optimization I: strip-mining for vectorization, parallel reduction.
  *
Optimization II: loop tiling, thread affinity.

Please note: You must complete CDT 101 before taking CDT 102.

Register for this workshop here<http://events.r20.constantcontact.com/register/event?oeidk=a07eao1gba177526b85&llr=kpiwi7pab>.

All workshops are offered free of charge.

Benjamin Recchie
Communications, Outreach, and Project Manager, Research Computing Center
The University of Chicago
6030 S. Ellis Ave., Room 130
Chicago, IL 60637
E: bcrecchi at uchicago.edu
T: 773.834.5546
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