[Colloquium] Fwd: Anwar Ghuloum from Intel Labs

Margery Ishmael marge at cs.uchicago.edu
Fri Dec 8 12:56:54 CST 2006


>> From: Umut Acar <umut at tti-c.org>
>> Date: December 8, 2006 11:19:10 AM CST
>> To: dbm at cs.uchicago.edu
>> Cc: Umut Acar <umut at tti-c.org>
>> Subject: Anwar Ghuloum from Intel Labs
>>
>> Dave,
>> here is the updated talk information.  Can you please post it?
>>
>> Umut
>>
>> --------------------------------------------------------------------- 
>> ---------------------------------------------
>> ----- Talk Announcement
>> --------------------------------------------------------------------- 
>> ---------------------------------------------
>>
>> -- Date: Tuesday, 12 December 2006
>> -- Place:  TTI-C (Toyota Technological Institute) Room 230 (just  
>> outside the elevators)
>>
>> -- Speaker: Anwar Ghuloum, Intel Labs
>> -- Talk Title: Programming Challenges for Many-Core Computing
>>
>> -- Host: Umut Acar (umut at tti-c.org).  Please let me know if you  
>> want to meet the speaker.
>>
>> -- Abstract
>>
>> Many-core architectures face significant hurdles to successful  
>> adoption by ISVs, and ultimately, the marketplace. One of the most  
>> difficult is addressing the programmability problems associated  
>> with parallel computing.  For example, it is notoriously difficult  
>> to debug a parallel application, given the potential interleavings  
>> of the various threads of control in that application.  Another  
>> problem is that predicting performance, even at coarse accuracy,  
>> is extremely inaccurate.   I will explain why a chip company like  
>> Intel is interested in advanced programming languages research and  
>> believes this is critical to adoption of many-core architectures.
>>
>> Intel’s Programming Research Lab is addressing these issues for  
>> both client and server computing, in particular media and gaming  
>> workloads.  We are implementing a high-level programming  
>> abstractions based on transactional memory, data parallel  
>> programming models and functional languages. In this talk, I will  
>> briefly discuss a language based on Nested Data Parallelism (NDP)  
>> called Ct.   NDP models have the advantage of being deterministic,  
>> meaning that the functional behaviors of sequential and parallel  
>> executions of an NDP program are always the same for the same  
>> input.  Data races are not possible in this model. Furthermore,  
>> NDP models have an easy to understand coarse performance model,  
>> which can be made more accurate for specific architectural  
>> families.   This enables the programmer to comprehend the  
>> performance implications of their code well-enough to make well- 
>> informed algorithmic choices.
>>
>>
>> -- Bio
>>
>> Anwar Ghuloum earned degrees at the University of California, Los  
>> Angeles (B.S., Computer Science and Engineering) and Carnegie  
>> Mellon University’s School of Computer Science (Ph.D., Computer  
>> Science, 1996), where his thesis introduced concepts of Nested  
>> Data Parallel idioms to traditional parallelizing compilers. Anwar  
>> has been a Senior Staff Scientist with Intel’s Programming Systems  
>> Lab since joining in early 2002, working on diverse topics such as  
>> optimizing memory system performance, parallel architecture  
>> evaluation, parallel language and compiler design, and multimedia  
>> applications.  Before that, he co-founded and was the CTO of a fab- 
>> less semiconductor startup called Intensys that built  
>> programmable, highly parallel image and video processors for the  
>> consumer electronics market. Prior to that, Anwar developed novel  
>> predictive drug design software for early lead optimization using  
>> 3D surface pattern recognition techniques for a biotech startup  
>> called MetaXen (acquired by Exelexis Pharmaceuticals).  He has  
>> also served as a post-doctoral research associate at Stanford  
>> University’s Computer Science department.  A recurring theme in  
>> Anwar’s work has been to 	bridge high-level application knowledge  
>> and low-level parallel architecture constraints with careful  
>> parallel language and compiler design.
>>
>>
>

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